Danh mục
Development
Web Development Data Storage Git Automation Database Design Web Scraping
Business
Business Analysis Communication Project Management Sales Forecasting Business Strategy Operations Management Human Resources Oil and Gas Industry
Finance & Accounting
IT & Software
Office Productivity
SAP Word Excel PowerPoint Excel VBA SharePoint
Personal Development
Persuasion Notion Workspace Mind Mapping
Design
Design Sketching Typography Game Design Digital Art zBrush 3D Animation
Marketing
SEO Marketing Strategy YouTube Marketing Digital Marketing Facebook Marketing Growth Hacking Twitter Marketing Instagram Marketing
Lifestyle
Beer Brewing Beauty Home Repair Energy Healing Bartending Leather Crafting Makeup Artistry Hypnotherapy
Music
Piano Guitar Singing Music Production Acoustic Guitar Fingerstyle Guitar Music Theory Bass Guitar
Duocmmo Tedu Tin học văn phòng Khoá học miễn phí Tất cả khoá học
Get link khoá học
Trang chủ
IT & Software
Hardware
SystemVerilog
SystemVerilog for Verification Part 2 : Projects

SystemVerilog for Verification Part 2 : Projects

Loại khoá học: Hardware

Verification of Common Peripherals, Memories, and Bus Protocol

image
50.000 VND
105 VND
Đầy Đủ Bài Giảng
Học Online Tiện Lợi
Kích Hoạt Nhanh 2-5 Phút
Thanh toán tự động
Được phép tải xuống

Tổng quan

Nội dung khoá học

Đánh giá

Mô tả

The VLSI industry can be divided into two branches, viz., design of RTL and verification of the RTL. Verilog and VHDL remain the popular choices for most design engineers working in RTL design. Functional verification could also be performed with the Hardware Description Language, but the Hardware Description Language has limited capabilities for performing code coverage analysis, corner case testing, and so on, and writing TB code may be impossible for complex systems at times.

SystemVerilog has become the primary choice of verification engineers to perform verification of complex RTL's. SystemVerilog object-oriented capabilities such as inheritance, polymorphism, and randomization allow users to find critical bugs with minimum effort.

Each complex system in FPGAs is built with the help of multiple subsystems. These subsystems can be either simple sequential components / simple combinational components / data communication protocols RTL / bus protocol RTL.

Once we understand strategies to perform verification of the common subsystems, you can easily perform verification of any complex system with the same logic.

Our objective for the course will be to build logic with the help of the fundamentals discussed in the first part of the course to perform verification of these common subsystems. We start our course by performing verification of data flipflops and FIFOs, then proceed to verification of common data communication protocols, viz., SPI, UART, and I2C. Finally, we will perform the verification of bus protocols, viz., ABP, AHB, AXI, and Whishbone protocol.

Bạn sẽ học được gì

Verification of Memories viz. FIFO

Verification of Bus Protocols viz. APB, AHB, AXI, Whishbone

Verification of Interface Communication Protocols viz. SPI, UART, I2C

Verification of Simple Compinational Block viz. Adder

Verification of Simple Sequential Block viz. Data Flipflop

Yêu cầu

  • Fundamentals of Verilog, Digital Electronics

Nội dung khoá học

9 sections

Verification Environment for D-FF

9 lectures
Course Pre-requisites
00:10
Summary
00:23
D-Flipflop P1
04:11
D-Flipflop P2
07:22
D-Flipflop P3
06:44
Design Code
00:24
TB Codes
03:46
A11
1 question
A12
1 question

Verification environment for First In First Out (FIFO)

7 lectures
Summary
00:18
FIFO P1
06:28
FIFO P2
06:00
FIFO P3
06:28
Design Code
00:46
TB code with comments
02:53
A21
1 question

Communication Protocol: Verification of Serial Peripheral Interface (SPI)

11 lectures
SPI Master P1
06:52
SPI Master P2
06:30
SPI Master P3
04:13
Design Code
00:39
TB Code
02:27
SPI with slave P1
05:30
SPI with slave P2
04:40
Design Code
01:01
Verilog TB
00:16
Testbench Code
03:00
A31
1 question

Communication Protocol: Verification of UART

8 lectures
UART P1
12:42
UART P2
03:06
UART P3
07:30
UART P4
03:19
UART P5
01:21
Design Code
01:21
TB Code
03:52
A41
1 question

Communication Protocol: Verification of I2C(Inter-Integrated Circuit)

11 lectures
Understanding start and stop conditions
05:46
I2C Write and Read Transactions
07:31
I2C Master FSM
04:01
I2C Master
21:56
I2C Slave
11:43
I2C Verification Environment P1
07:00
I2C Verification Environment P2
04:54
I2C Verification Environment P3
03:23
Design Code
06:35
TB Code
02:49
A51
1 question

Bus Protocol: Verification of APB_RAM

21 lectures
Understanding Advanced Peripheral Bus Signals
06:36
Understanding APB Transactions P1
05:16
Understanding APB Transactions P2
06:51
Understanding Design
16:01
Code
00:49
Transaction Class P1
04:05
Transaction Class P2
11:31
Code
00:34
Generator Class
06:52
Code
00:18
Adding Interface
00:59
Driver Class P1
12:11
Driver Class P2
03:55
Code
01:32
Monitor Class
07:05
Code
00:34
Scoreboard Class
05:44
Code
00:27
Environment and Testbench Top
09:26
Code
00:40
Complete Code
05:02

Bus Protocol: Verification of AXI Memory

26 lectures
Understanding AXI Channels
04:12
Understanding Write address Signals
10:27
Understanding Write Data Signals
02:46
Understanding Read Signals
03:01
Understanding Design P1
07:13
Understanding Design P2
04:33
Understanding Burst Mode P1
08:00
Understanding Burst Mode P2
08:37
Summary
02:19
Implementing FIXED Mode
04:47
Implementing INCR Mode
03:09
Implementing WRAP Mode
15:47
Understanding Design P3
18:52
Understanding Design P4
05:47
Understanding Design P5
09:04
Understanding Design P6
14:48
Transaction Class
05:23
Generator Class
09:41
Driver Class P1
15:21
Driver Class P2
04:50
Driver Class P3
05:36
Driver Class P4
08:03
Monitor Class
05:51
Scoreboard Class
05:53
Testbench Top
08:23
Code
17:59

Bus Protocol: Verification of AHB Memory

18 lectures
Understanding AHB Signals P1
10:59
Understanding AHB Signals P2
02:57
Understanding Design P1
Processing..
Understanding Design P2
09:31
Understanding Design P3
09:59
Understanding Design P4
19:01
Understanding Design P5
11:13
Transaction Class
08:11
Generator Class
04:54
Driver Class P1
02:22
Driver Class P2
14:41
Driver Class P3
05:50
Monitor Class
14:22
Scoreboard Class
06:25
Verifying different Burst Modes P1
02:53
Verifying different Burst Modes P2
07:22
Design Code
05:40
Testbench Code
11:24

Bus Protocol: Verification of Whishbone Memory

10 lectures
Understanding Protocol
11:13
Understanding Design
10:46
Transaction Class
06:38
Generator Class
03:31
Driver Class
08:49
Monitor Class
04:25
Scoreboard Class
03:15
Testbench Top
03:40
Design Code
00:39
Testbench Code
02:49

Đánh giá của học viên

Chưa có đánh giá
Course Rating
5
0%
4
0%
3
0%
2
0%
1
0%

Bình luận khách hàng

Viết Bình Luận

Bạn đánh giá khoá học này thế nào?

Khoá học liên quan

Embedded Linux Using Yocto Part 2

Embedded Linux Using Yocto Part 2

80 VND
50.000 VND
Embedded Linux using Yocto Part 3

Embedded Linux using Yocto Part 3

85 VND
50.000 VND
Embedded Linux using Yocto

Embedded Linux using Yocto

80 VND
50.000 VND
Viết ứng dụng bán hàng với Java Springboot/API và Angular

Viết ứng dụng bán hàng với Java Springboot/API và Angular

25 VND
50.000 VND
An ninh mạng cho người mới bắt đầu

An ninh mạng cho người mới bắt đầu

25 VND
50.000 VND
An Entry-Level Course on Analog and Digital Microelectronics

An Entry-Level Course on Analog and Digital Microelectronics

75 VND
50.000 VND
DATA CENTER - TRUNG TÂM DỮ LIỆU: HỆ THỐNG ĐIỆN.03 - CB08

DATA CENTER - TRUNG TÂM DỮ LIỆU: HỆ THỐNG ĐIỆN.03 - CB08

30 VND
50.000 VND
Starting an ISP with MikroTik

Starting an ISP with MikroTik

25 VND
50.000 VND
MikroTik Security Engineer with LABS

MikroTik Security Engineer with LABS

25 VND
50.000 VND
MikroTik Traffic Control with LABS

MikroTik Traffic Control with LABS

25 VND
50.000 VND
MikroTik Routing Engineer with LABS

MikroTik Routing Engineer with LABS

25 VND
50.000 VND
ISP Core Network Setup with MikroTik

ISP Core Network Setup with MikroTik

25 VND
50.000 VND
EF Core and .NET 6: Zero to Pro with ASP NET Web Api

EF Core and .NET 6: Zero to Pro with ASP NET Web Api

25 VND
50.000 VND
DevOps Beginners to Advanced with Projects

DevOps Beginners to Advanced with Projects

120 VND
50.000 VND
[2023] Master Spring MVC with Java for Beginners

[2023] Master Spring MVC with Java for Beginners

25 VND
50.000 VND
Javascript cho người mới bắt đầu

Javascript cho người mới bắt đầu

120 VND
50.000 VND
image

Đăng ký get khoá học Udemy - Unica - Gitiho giá chỉ 50k!

Get khoá học giá rẻ ngay trước khi bị fix.

Get khoá học cho tôi