Mô tả

Are you a beginner or an enthusiastic hobbyist interested in digital circuits design using the Verilog Hardware Description Language? Did you try to learn Verilog HDL before, but found it very challenging? Are you curious if you have what it takes to become a digital chip designer or a functional verification engineer? Then you're in the right place!

Verilog Hardware Description Language easy as A,B,C

You'll learn the basics of digital circuits theory and we'll focus most of our energy on implementing practical coding examples with real digital circuits using Verilog. You will graduate this course with a strong foundation in Verilog HDL for both Digital Design and Functional Verification.

From the Digital Design perspective, you'll be able to:

  • start from a digital circuit diagram / schematic and implement synthesizable Verilog code for ASIC / FPGA

  • start from a functional description and implement synthesizable Verilog code for ASIC / FPGA

From the Functional Verification perspective, you'll be able to:

  • understand a functional description of a digital circuit and create stimuli for it

  • implement a self-checking testbench to validate the functionality of a digital circuit

You will easily differentiate between different Verilog coding styles (structural, dataflow, behavioral) and how to use them to design synthesizable digital circuits. You'll see just how easy modeling digital circuits using Verilog is!

At the end of the course you'll master Verilog industry-level coding techniques to get the best results for digital design or verification.

Learn how to use an industry-level Verilog HDL simulator

Simulations are a critical part in designing modern digital chips, thus you will install and learn how to use Modelsim - Intel FPGA Edition (free version for academic purpose).  You will be able to create projects, simulate your Verilog code, and interpret the outputs using an world-class simulator.

Course Overview

This course is tailored for beginners who are interested in digital microelectronics, digital circuit design and verification. The course contains more than 158 bite-sized lectures out of which more than half are hands-on exercises labeled Action Time. Each Action Time has downloadable resources which you can simulate immediately using Modelsim. Most of these sections also contain challenges for you, so you'll write extra code that extends beyond the initial functionality.

Your first Verilog examples will be similar to a normal programming language (like C) to learn the operators, and, step-by-step, we'll advance together to the Hardware Description Language constructs, where Verilog procedures execute in parallel.

You'll learn how to use Verilog for combinational and sequential logic and how to combine the Structural / Dataflow / Behavioral coding styles to obtain digital circuits with a specific functionality. Your circuits will get more complex as you advance, some of them being composed of a hierarchy of sub-circuits.

Verilog combinational circuits you will implement during the course :  logic gates, adders, comparator, binary encoder / decoder, priority encoder, multiplexers / de-multiplexers, seven segment display decoder, Arithmetical Logical Unit (ALU), etc...

Verilog sequential circuits you will implement during the course: flip-flops, latches, shift registers (PIPO, PISO, SIPO, SISO), Linear Feedback Shift Registers, synchronous counters, frequency dividers, Sequence Detector etc...

Next, you'll experiment with Verilog functions and tasks and how to use them in testbenches and design. 

In the final chapters you will design memories (SRAM and ROM), Finite State Machines, and more complex circuits like a FIFO and even a data encryption module.

A workflow with destination SUCCESS!

  1. We start from real engineering problems and understand how a digital circuit solves that problem.

  2. You are presented a real digital circuit, how it is used in the real world, then how to model and test it using Verilog.

  3. You simulate it using Modelsim, and next I walk you through the results interpretation.

We do this process together every single time....  I explain the story behind the Verilog code so that, at the end of the course, you will be able to write the Verilog code behind the story.

Why learn Verilog HDL?

Chances are more than 50% that all the chips in the devices around you were designed with Verilog.

Working as a Digital Design or a Functional Verification engineer means to design today the technologies of tomorrow. This translates into having an exciting and challenging job with a great impact in the world. Since less than 2% of engineers choose this path and the semiconductor industry has never been busier, I'm pretty sure you will find yourself a good place in it.

Verilog is a good foundation for learning SystemVerilog, which is a very popular object-oriented design and verification language in the semiconductor industry.

Why did I create this course?

As an engineering student, I found it quite challenging to learn Verilog because it has a very steep learning curve and you need lots of know-how to be able to run even a simple example. Because of this, most students give up learning Verilog for a career in Digital Design or Verification and this also negatively impacts their academic results.

After 10+ years of industry experience, thousands of hours in Verilog, and academic research, I feel I've found the missing puzzle pieces that I didn't have back in the days. This course will show you the beauty and simplicity of digital circuits design using Verilog!

Ready? Set... GO!

Thank you for your interest in Verilog HDL for Digital Circuits Design and Functional Verification!

Ready to embark on your journey in mastering the basics of Verilog HDL for digital design and verification? Let's start this wonderful adventure!

Bạn sẽ học được gì

Master the basics of Verilog language for designing synthesizable digital circuits for ASIC / FPGA

Differentiate between Verilog structural / dataflow / behavioral design styles and how / when to use them in Digital Design and Verification

Implement combinational and sequential digital circuits using Verilog HDL starting from schematics or functional specifications

Create and simulate a Verilog testbench for a digital circuit starting from its functional specifications

Examine the behavior of a digital circuit receiving stimulus in a testbench, using an industry-level simulator (free for academic purposes)

Explicit visual explanations for the 80+ downloadable code examples, circuits, and testbenches offering you increased retention and accelerated learning

Yêu cầu

  • Basic notions of programming languages (like C / C++/ Python)
  • Interest in hardware description languages. You will learn everything about Verilog HDL for Design and Verification in this course
  • Interest in digital microelectronics, digital circuits design and verification

Nội dung khoá học

12 sections

Introduction

7 lectures
Welcome!
03:02
Course overview
03:31
What is Verilog HDL?
01:12
Understand Abstraction Levels
02:25
Discover the Modern Digital Design Flow
02:10
Q&A: Will I be able to apply for a job after learning the Verilog fundamentals?
00:38
Verilog HDL basics
3 questions

Install the Simulator

7 lectures
Discover the Verilog Simulation
01:10
Install Intel Quartus Prime Lite and Modelsim
01:23
Q&A 1: Install Intel Quartus Prime Lite and Modelsim
00:56
Q&A 2: MAC users - Install Intel Quartus Prime Lite and Modelsim
00:30
Action Time - Hello World using Verilog
02:53
Print your username and course start date
1 question
Congratulations!
00:39

Verilog Data Types and Operators

42 lectures
Verilog Data types overview
01:12
Action time - sum and product
02:03
Q&A 1: Action Time - sum and product
00:48
Q&A 2: Action Time - sum and product
00:34
Hardware Description Language data types
01:13
Action time - Multiple procedures
02:03
Q&A: Action Time - Multiple Procedures
00:33
What are Literal Values?
00:52
Action time - Literal values
01:45
Q&A: Action time - Literal Values
00:37
Data types, procedures and format specifiers
5 questions
Vectors in Verilog
00:45
Action time - Vectors
02:00
Verilog Operators - Bit-wise
01:19
Action Time - Bit-wise operators
01:32
Q&A: Action Time - Bit-wise operators
00:32
Verilog Operators - Reduction
00:28
Action Time - Reduction operators
01:25
Q&A: Action Time - Reduction Operators
00:09
Verilog Operators - Logical
00:44
Q&A: Verilog Operators - Logical
00:49
Action Time - Logical Operators
00:59
Action Time - Logical Operators usage
01:15
Q&A: Action Time - Logical Operators usage
02:16
Verilog Operators - Arithmetic
00:17
Action Time - Arithmetic Operators
00:39
Verilog Operators - Shift
00:50
Action Time - Shift Operators
00:58
Verilog Operators - Relational
00:30
Action Time - Relational Operators
00:56
Verilog Operators - Equality
00:51
Action Time - Equality Operators
00:30
Verilog Operators - Conditional
00:33
Action Time - Conditional Operator
01:05
Verilog Operators - Concatenation
00:32
Action Time - Concatenation Operator
01:14
Verilog Operators - Replication
00:46
Action Time - Replication Operator
01:25
Verilog Operators - Precedence
00:30
Action Time - Operators Precedence
01:00
Verilog Operators
5 questions
Congratulations!
00:23

Verilog Module

8 lectures
Verilog Module - the basics
02:51
Action time - Do your first testbench
03:02
Q&A: Action Time - Do your first testbench
01:00
Remember!
00:28
What is a Testbench Architecture
00:55
Discover Time and Waveforms
00:51
Action Time - Generate Waveforms
01:21
Verilog Module
5 questions

Verilog Design Styles

23 lectures
What are HDL Design Styles?
00:51
Verilog Structural Design
00:54
Action Time - half adder structural
02:46
Verilog Dataflow style
00:36
Action Time - half_adder dataflow
01:44
Verilog_Behavioral_style
02:40
Remember!
00:26
Action Time - Initial Procedures
01:09
Q&A: Action Time - Initial Procedures
00:23
Verilog Design Styles
5 questions
Action Time - half_adder behavioral
01:08
Design a 1bit full_adder
01:12
Action Time - full_adder structural
01:45
Q&A: Action Time - full_adder_structural
00:15
Action Time - full_adder dataflow
01:01
Q&A: Action Time - full_adder_dataflow
00:18
Action Time - full_adder behavioral
01:29
Design a 4bit full_adder
00:50
Action Time - 4bit_full_adder structural
02:45
Action Time - 4bit_full_adder dataflow
01:27
Action Time - 4bit_full_adder behavioral
00:56
Q&A : Action Time - 4bit_full_adder behavioral
00:21
Congratulations!
00:31

Verilog Structural Design

15 lectures
What is Structural Design?
00:43
Verilog Built-in_Primitives
01:40
Action Time - Built-in_gates
00:59
Discover the Multiplexer
01:50
Action Time - 1bit_mux
01:50
Discover the Demultiplexer
01:22
Action Time -1bit_demux
01:53
The Tri-state buffer
00:47
Action Time - tri-state_buffer
01:11
How to implement a multiplexer using tri-state buffers
00:48
Action Time - mux_tri-state
01:44
Discover the 1bit Comparator
00:37
Action Time - 1bit_comparator
02:13
Remember!
00:30
Verilog Structural Design
4 questions

Verilog Combinational Design

31 lectures
What is Combinational logic?
01:28
Discover Continuous assignments
00:45
Action Time - Continuous assignments
01:28
Action Time - Adder Tree
01:56
Discover Procedural Assignments
01:19
Action Time - Tree Adder Procedural
01:35
Discover the Nbit Adder
00:31
Action Time - Nbit Adder
02:16
Q&A: Action Time - Nbit Adder
00:55
Action Time - Nbit Comparator
02:09
Differentiate between binary encoders and decoders
01:15
Action Time - Nbit Decoder
02:06
How to use multiple binary decoders
00:45
Action Time - 4to16 binary Decoder
02:46
Action Time - 8to3 Encoder
02:27
Q&A: Action Time - 8to3 Encoder
00:48
What is a Priority Encoder
01:20
Action Time - Priority Encoder1 4to2
01:42
Action Time - Priority Encoder2 4to2
01:32
Discover bus Multiplexers
01:05
Q&A: Discover bus Demultiplexers
01:22
Action Time - mux_4x_nbit
01:57
Q&A: Action Time - mux_4x_nbit
00:33
Discover bus Demultiplexers
00:54
Action Time - demux_4x_nbit
02:29
Master the Seven Segment Display Decoder
01:58
Action Time - HEX 7segment decoder
02:19
How to use digital logic for arithmetic operations
01:53
Action time - Design an Arithmetical Logical Unit (ALU)
04:32
Remember!
00:27
Verilog Combinational Design
5 questions

Verilog Sequential Design

32 lectures
Sequential Logic Basics
01:54
Action Time - Clocks Generator
02:42
Types of Sequential Digital Logic
01:30
Action Time - The D_Latch
01:38
Action Time - D_Latch_reset_n
01:38
Q&A: How to code 'if ... else ...' statements in Verilog
00:10
Basics of edge-triggered logic
02:13
Action Time - D_Flip_Flop_sync_rstn
04:00
Q&A: Action Time - D_Flip_Flop_sync_rstn
00:37
Action Time - D_Flip_Flop_async_rstn
01:21
Remember!
00:44
Discover the Shift Register
01:36
Action Time - Shift_Reg_PIPO
02:24
Action Time - Shift_Reg_SIPO
03:03
Action Time - Shift_Reg_SISO
01:53
Action Time - Shift_Reg_PISO
03:48
Action Time - Shift_Left_Right_Reg
03:22
Discover the Linear Feedback Shift Register
01:14
Action Time - Linear Feedback Shift Register
03:28
Discover Synchronous Counters
01:35
Action Time - Nbit Counter
02:09
Action Time - Nbit up/down Counter
03:13
Action Time - Modulo_N Counter
02:48
Discover Digital Frequency Dividers
01:33
Action Time - Clock Divider Nbit
02:07
Q&A: Action Time - Clock Divider Nbit
00:52
Action Time - Clock Divider by 3
03:16
Q&A 1: Action Time - Clock Divider by 3
01:03
Q&A 2: Action Time - Clock Divider by 3
01:12
Q&A 3: Action Time - Clock Divider by 3
00:47
Q&A : Difference between Blocking and Non-blocking statements
01:00
Verilog Sequential Design
4 questions

Verilog Functions and Tasks

15 lectures
Verilog Functions Basics
01:35
Action Time - Verilog Functions1
01:08
Action Time - Verilog Functions2
00:57
Discover Verilog Recursive Functions
01:12
Action Time - Verilog Functions Factorial
01:23
Action Time - Verilog Functions Fibonacci
00:58
Action Time - Nbit Comparator Function
02:35
Verilog Tasks Basics
00:50
Action Time - Verilog Tasks Distance Conversion
00:57
Action Time - Verilog Tasks Control Shift Reg
01:36
Why our code looks like software
00:58
Action Time - Shift Reg PIPO buggy
03:30
Discover Automated Verification
01:41
Action Time - ALU self-checking testbench
04:52
Verilog Functions and Tasks
5 questions

Verilog Memory Design

6 lectures
Basics of Semiconductor Memory
02:00
Action Time - Single Port Async Read SRAM
04:30
Action Time - Single Port Sync Read SRAM
02:05
Action Time - Dual Port Async Read SRAM
04:39
Action Time - Single Port Sync Read ROM
03:09
Verilog Memory Design
5 questions

Verilog State Machines

7 lectures
Discover Finite State Machines
02:59
Action Time - Metro turnstile (Mealy FSM)
06:57
Action Time - Special Semaphore (Mealy FSM)
09:35
Basics of Sequence Detectors
00:50
Action Time - Sequence Detector NON Overlaping
02:50
Action Time - Sequence Detector Overlaping
01:03
Verilog Mealy FSM Template
02:29

Verilog Design Examples

6 lectures
Discover the First In First Out (FIFO) circuit
01:43
Action Time - Synchronous FIFO
07:07
Action Time - Data Transfer FSM
10:00
Basics of Data Ecryption
02:16
Action Time - Design a Stream Cypher
10:20
Congratulations!
00:44

Đánh giá của học viên

Chưa có đánh giá
Course Rating
5
0%
4
0%
3
0%
2
0%
1
0%

Bình luận khách hàng

Viết Bình Luận

Bạn đánh giá khoá học này thế nào?

image

Đăng ký get khoá học Udemy - Unica - Gitiho giá chỉ 50k!

Get khoá học giá rẻ ngay trước khi bị fix.