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Teaching & Academics

Verilog HDL Programming

System Design using Verilog

System Design using Verilog

Loại khoá học: Engineering

FPGA Based Design

50.000 VND

25 VND

Đầy Đủ Bài Giảng

Học Online Tiện Lợi

Kích Hoạt Nhanh 2-5 Phút

Thanh toán tự động

Được phép tải xuống

Mô tả

After completion of this course learners will be able to:

(1) Understand the concepts design metrics which are to be optimized by a design engineer

(2) Understand the concepts of IC design technology

(3) Understand the implementation of logic using Fixed Function IC Technology, Full Custom ASIC Technology, and Semi-Custom ASIC Technology

(4) Understand the advantages and disadvantages of implementation of logic using Fixed Function IC Technology, Full Custom ASIC Technology, and Semi-Custom ASIC Technology

(5) Understand the concept of implementation of logic in PLDs

(6) Understand the concept of implementation of logic in FPGA

(7) Understand the IC design flow

(8) Understand the role of HDL in system design

(9) Understand the concepts of various Verilog language constructs

(10) Understand various operators and their uses in Verilog coding

(11) Understand how to use Xilinx software for writing a Verilog code

(12) Understand how to use Xilinx software for simulating a Verilog code

(13) Understand how to use Xilinx software for implementing a Verilog code

(14) Implement combinational logic by using behavioral modeling style

(15) Implement combinational logic by using dataflow modeling style

(16) Implement combinational logic by using structural modeling style

(17) Implement sequential logic by using behavioral modeling style

(18) Implement sequential logic by using dataflow modeling style

(19) Implement sequential logic by using structural modeling style

(20) Implement logic by using mos transistors

Bạn sẽ học được gì

Verilog coding for digital circuits

Yêu cầu

No

Nội dung khoá học

12 sections

IC Design Technology

10 lectures

Design Metrics

14:56

Fixed Function IC Technology

24:46

Full Custom ASIC Technology

31:58

Semi-Custom ASIC Technology

25:24

HDL Role in System Design

51:37

PLD Technology (PLA)

30:52

PLD Technology (PAL)

17:20

FPGA (Architecture)

37:54

FPGA (Logic Implementation Examples)

29:01

Challenge Your Self - 1

5 questions

Introduction to Verilog and Xilinx Software

10 lectures

Introduction to Verilog

23:25

Level of Abstraction

20:41

Introduction to Xilinx Software

15:04

Data Types (Net Types)

24:40

Data Types (Register Types)

34:09

Operator (Bitwise operators)

28:21

Operator (Logical & Reduction)

32:21

Operator (Arithmetic, Relational & Shift)

29:11

Operator (Concatenation, Conditional & Replication)

27:23

Challenge Your Self – 2

3 questions

Introduction to different level of modeling

3 lectures

Introduction to Structure Level Modeling

46:54

Introduction to Behavioural Level Modeling

41:39

Introduction to Dataflow Level Modeling

35:52

Testbench

3 lectures

Test Bench-(Part I)

48:38

Test Bench -(Part II)

35:15

Test Bench-(Part III)

27:39

Structure Modeling

4 lectures

Structure Modeling (2 to 1 Multiplexer)

31:41

Structure Modeling (2 to 4 Decoder)

23:40

Structure Modeling (3-Bit Adder) Part - I

29:32

Structure Modeling (3-Bit Adder) Part - II

19:56

Behavioural Modeling

13 lectures

Procedural Statements

45:22

Sequential Statements (if-else) Part-I

33:50

Sequential Statements (if-else) Part-II

22:55

Sequential Statements (if-else) Part-III

33:21

2 to 4 Decoder using if-else Statement

18:13

Comparator using “if-else” Statement

26:16

Software demonstration of Comparator

09:42

2 to 1 Multiplexer using “case” Statement

13:38

4 to 1 Multiplexer using “case” Statement

15:10

2 to 4 Decoder using “case” Statement

16:31

1 Bit Comparator using “case” Statement

18:02

BCD to 7 Segment Decoder using “case” Statement

26:05

Sequential Statements - (loop)

35:22

Behaviourl Model - Sequential Circuits

7 lectures

Verilog code of D Flip Flop

46:28

Verilog code of JK Flip Flop

44:09

Verilog code of T Flip Flop

23:37

Verilog code of 3 Bit Counter

27:46

Parallel In Parallel Out Register

29:50

Serial In Parallel Out Register

25:10

Serial In Serial Out Register

29:19

Multiple Always Block

3 lectures

Multiple always block - (Example)

26:18

Multiple always block – (D Flip Flop)

18:40

Multiple always block - (2 to 4 Decoder)

33:22

Blocking and Non-blocking Statements

2 lectures

Blocking Statement

27:15

Non-Blocking Statement

30:30

Few Examples of Combinational Circuits

5 lectures

Verilog Model of Full Subtractor

28:16

Binary to Gray Converter

31:48

Gray to Binary Converter

37:13

Verilog Code of 1 to 2 Demultiplexer

13:52

Priority Encoder

29:57

Switch Level Modeling

4 lectures

“cmos” Switch (Part I)

42:33

“cmos” Switch (Part II)

17:44

“cmos” Switch (Part III)

15:16

“cmos” Switch (Part IV)

11:55

User Defined Primitive (UDP)

4 lectures

UDP (Part-1)

18:34

UDP (Part-2)

29:56

UDP (Part-3)

15:23

UDP (Part-4)

16:14

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