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Embedded Systems

Embedded System Design with Microblaze and Vitis IDE

Embedded System Design with Microblaze and Vitis IDE

Loại khoá học: Hardware

Using Xilinx Vivado Design Suite and Vitis 2020.2

50.000 VND

1.199.000 VND

Đầy Đủ Bài Giảng

Học Online Tiện Lợi

Kích Hoạt Nhanh 2-5 Phút

Thanh toán tự động

Được phép tải xuống

Mô tả

A faster Reconfigurable system makes FPGA a prominent choice for a large set of applications, but Hardware alone is incomplete without smart software synchronizing all the events fruitfully to achieve the desired Application. This course covers fundamentals of Popular Xilinx drivers viz. UART, AXI Timers, UART16550, AXI GPIO, AXI BRAM, etc. The course also illustrates the usage of the AXI interrupt controller for handling Interrupts. Also to felicitate incorporation of Hardware accelerators with Microblaze based design few examples on building Custom AXI Peripherals are also included. Software and Hardware Debugging, Profiling fundamentals are demonstrated with Microblaze to felicitate performance measurement.

The Microblaze is an FPGA-based Soft Processor capable of executing single instruction per cycle with few exceptions. The MicroBlaze interconnect is reconfigurable capable of communicating with a large set of peripherals to fit most of the medium-scale applications. It allows configuration of cache size, pipeline depth, peripherals, memory management unit, and bus interface suitable to fit different application requirements. As systems complexities are growing day by day, Microblaze will play central role in the non-Zynq based FPGA families whereas it will be the best light-weight alternative working in tandem with the Zynq hard processor for Zynq and Ultrascale based FPGA families.

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Nội dung khoá học

10 sections

Installation : Vivado 2020.2

4 lectures

Downloading Setup File

03:57

Choosing Installation Settings

02:28

LIC File

00:00

Adding License

00:56

Getting Started

11 lectures

Agenda

00:54

Design Flow Steps P1

11:48

Design Flow Steps P2

01:44

Design Flow Steps P3

06:27

Fundamentals: Project Types

03:42

Fundamentals P2 : Flow Navigator

08:18

Fundamentals P3: Useful files in Project Directory

03:43

Fundamentals P3: How to update Hardware Platform P1

01:44

Fundamentals P3: How to update Hardware Platform P2

01:53

TCL Script for automation

09:09

Different Reporting Mechanism

10:08

Simple Peripherals

17 lectures

Agenda

01:43

Fundamentals of XIL Drivers P1

04:14

Fundamentals of XIL Drivers P2

08:10

Fundamentals of XIL Drivers P3

03:36

Writing Data to GPIO P1

03:55

Writing Data to GPIO P2

00:51

Writing Data to GPIO P3

13:18

Code

00:14

Reading Data from GPIO P1

01:22

Reading Data from GPIO P2

05:32

Code

00:15

Using Dual Channel of GPIO P1

03:01

Using Dual Channel of GPIO P2

13:39

Code

00:17

Multiple Instances of GPIO P1

03:04

Multiple Instances of GPIO P2

11:58

Code

00:18

Intermediate Peripherals

12 lectures

Agenda

02:05

Sending Data to UART P1

01:47

Sending Data to UART P2

16:01

Code

00:17

Receiving Data from UART

07:00

Code

00:20

Multiple Instance of UARTLITE P1

03:45

Multiple Instance of UARTLITE P2

09:32

Code

00:32

Working with UART16550 P1

02:18

Working with UART16550 P2

12:47

Code

00:20

Working with Timers

22 lectures

Agenda

00:32

Using AXI Timer P1

03:08

Using AXI Timer P2

19:31

Code

00:17

How we observe the Current Count Value

04:05

Using Auto Reload Mode

05:37

Code

00:37

Using both Timers

08:44

Code

00:24

Using PWM : 50% Duty Cycle P1

05:18

Using PWM : 50% Duty Cycle P2

02:13

Using PWM : 50% Duty Cycle P3

15:13

Code

00:16

Varying Duty Cycle

05:11

Code

00:17

Fading Effect

04:38

Code

00:24

AXI Timebase Watchdog Timer P1

03:48

AXI Timebase Watchdog Timer P2

06:11

Code

00:15

Mulitple Event with WDT

02:29

Code

00:16

Profiling

6 lectures

Agenda

00:58

Profile with AXI Timer P1

01:25

Profile with AXI Timer P2

07:11

SDK Profiler P1

03:36

SDK Profiler P2

08:37

Code

00:19

Memory Resources

5 lectures

Understanding Byte Addressable and Word Addressable

08:20

Adding BRAM IP to Block Design

03:02

BRAM Transactions using pointers

12:10

BRAM Transactions using XIL_IO Drivers

06:28

Code

00:32

Debugging Technique

4 lectures

Hardware Debugging : Integrated Logic Analyzer P1

05:32

Hardware Debugging : Integrated Logic Analyzer P2

10:16

Hardware Debugging : Integrated Logic Analyzer P3

01:16

Software Debugging : Serial Window

03:40

Interrupts

12 lectures

Agenda

00:52

Interrupt with GPIO P1

04:05

Interrupt with GPIO P2

24:06

Code

00:35

AXI Timer Interrupt P1

02:28

AXI Timer Interrupt P2

13:06

Code

00:26

Interrupt with WDT P1

04:01

Interrupt with WDT P2

10:17

Code

00:27

Reset with WDT

03:12

Code

00:26

Building Custom AXI Peripherals for Microblaze

8 lectures

Agenda

01:21

Create SLAVE AXI LITE Interface P1

11:36

Create SLAVE AXI LITE Interface P2

07:58

Adding Port to Slave AXI LITE Interface P1

07:45

Adding Port to Slave AXI LITE Interface P2

02:11

Adding Port to Slave AXI LITE Interface P3

04:51

Create AXI Stream Interface P1

19:46

Create AXI Stream Interface P2

03:15

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