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Zynq FPGA

Embedded System Design with Xilinx ZYNQ SoC and SDK

Embedded System Design with Xilinx ZYNQ SoC and SDK

Loại khoá học: Hardware

Using Xilinx Vivado Design Suite 2019.1 or Lower

50.000 VND

79 VND

Đầy Đủ Bài Giảng

Học Online Tiện Lợi

Kích Hoạt Nhanh 2-5 Phút

Thanh toán tự động

Được phép tải xuống

Mô tả

Xilinx Zynq SoC's are know to provide maximum performance per watt along with maximum reconfiguration flexibility. Zynq family features Dual-Core ARM Cortex A9 processors tightly coupled with the 7-series FPGA to enable faster communication interfaces development with ARM Design flow and hardware acceleration. Zynq devices are available in two categories viz. Zynq-7000s family FPGA for the cost-effective application such as IoT related applications while Zynq 7000 family FPGA are best for high-performance applications such as Embedded Vision etc. The Zynq 7000s comes with Single core ARM while Zynq 7000 comes with Dual-Core ARM.

This course covers fundamentals of Popular Xilinx drivers viz. UART, AXI Timers, UART16550, AXI GPIO, AXI BRAM, etc. The course also illustrates the usage of the AXI interrupt controller for handling Interrupts. Also to felicitate incorporation of Hardware accelerators with Zynq based design few examples on building Custom AXI Peripherals are also included. Software and Hardware Debugging, Profiling fundamentals are demonstrated with Zynq to felicitate performance measurement.

This course will create the foundation necessary to quickly start building applications on Zynq FPGA devices without prior experience in this domain. The entire course is a Lab-based course with a major focussed on building skills necessary to handle simple peripherals such as GPIO, Intermediate Peripherals such as UART PS, AXI BRAM, and complex Peripherals such as AXI Interrupt Controller, AXI Timers, GIC etc.

Bạn sẽ học được gì

Embedded System Design flow using Zynq AP SoC

Development of C applications for Zynq Devices

Fundamentals strategies to use Xilinx Drivers

Software and Hardware Debugging Strategies

Software Profiling

Working with Interrupts

Yêu cầu

Understanding of Digital Electronics
Fundamentals of Computer Architecture
Fundamentals of C

Nội dung khoá học

11 sections

Installing Vivado

10 lectures

Course Framework

06:27

Agenda

01:25

Tools used in the course

04:04

Recommendation

00:11

Installation Part 1

02:32

Installation Part 2

03:35

Xilinx LIC file

00:00

Adding Licencse

01:19

Digilent Board files: Download this before proceeding to the next Video

00:00

Adding Digilent Boards and Hardware Connection

01:10

Toolchain Configuration

14 lectures

Agenda

00:54

Introduction P1

10:41

Introduction P2

05:51

Code and BD

00:08

Fundamental P1 : Project Types

03:42

Fundamentals P2 : Flow Navigator

08:18

Fundamentals P3 : Board Presets

08:56

Fundamentals P4 : When you need to add I/O Constraint

07:58

Fundantals P5 : When you need to add I/O Constriaints

04:11

Understanding useful Files added to Project Directory

04:14

How to use TCL Script for BD automation

08:39

Fundamentals of SDK P1

05:25

Fundamentals of SDK P2

03:53

Fundamentals of Reporting Mechanism

11:00

Getting Started with Simple Peripherals : GPIO

26 lectures

Agenda

01:29

Zynq Intro

00:50

Zynq Peripherals

00:56

Ways to Communicate data between PS and Peripherals P1

04:02

Ways to Communicate data between PS and Peripherals P2

11:00

Fundamentals of XIL Drivers P1

04:14

Fundamentals of XIL Drivers P2

08:10

Fundamentals of XIL Drivers P3

03:36

Demonstration of XIL Drivers

08:07

Using MIO LED P1

04:38

Using MIO LED P2

12:34

C Code : MIO LED

00:16

Using MIO GPIO Input and Output

08:10

C Code : MIO BTN AND LED

00:18

Using GPIO EMIO LED P1

08:50

Using GPIO EMIO LED P2

14:08

ZYNQ EMIO LED C Code

00:24

Using GPIO EMIO LED AND BTN P1

06:43

Using GPIO EMIO LED AND BTN P2

13:21

Code: GPIO LED and SWITCH

00:37

Using AXI GPIO IP :Single Channel P1

08:28

Using AXI GPIO IP :Single Channel P2

15:56

CODE: AXI GPIO Single Channel

00:19

Using AXI GPIO IP : Multiple Channels P1

02:22

Using AXI GPIO IP : Multiple Channels P2

10:31

Code

00:16

Getting started with Intermediate Drivers : UARTPS

11 lectures

Agenda

00:22

Overview

05:19

UART with MIO P1

05:54

UART with MIO P2

13:50

UART with MIO P3

09:10

Code : UART MIO

00:21

MIO : Using UART0 and PMOD to extend Capabilities

06:51

EMIO : Performing connection to External Hardware / PL to UART

08:16

EMIO : Using AXI UARTLITE P1

04:24

EMIO : Using AXI UARTLITE P2

14:12

EMIO : Using AXI UARTLITE P3

02:28

Getting started with Intermediate Drivers : Understanding Timers

21 lectures

Agenda

01:50

Timers/Counters in Zynq Processing System

03:15

CPU Watchdog Timer P1

02:51

CPU Watchdog Timer P2

12:36

CPU Watchdog Timer P3

10:30

Code

00:19

CPU 32-bit Private Timer

14:52

Code

00:19

CPU 32-bit Timer : Use of Auto-reload Mode

02:52

Code

00:20

CPU 32-bit Timer : Use of Prescalar

05:18

Code

00:19

TTC in Polled Mode P1

04:06

TTC in Polled Mode P2

06:53

TTC in Polled Mode P3

15:34

Code

00:33

TTC and GPIO MIO LED in Polled Mode

08:40

Code

00:38

Working with PL Timer : AXI Timer IP P1

03:37

Working with PL Timer : AXI Timer IP P2

15:21

Code

00:22

Software and Hardware Debugging

15 lectures

Agenda

00:48

Using Serial Window for Debugging

04:27

Breakpoint P1

02:26

Breakpoint P2

06:02

Breakpoint P3

03:56

Breakpoint P4

05:30

Breakpoint P5

08:03

Using Memory Content Viewer

05:19

Using XSCT Console

09:43

ILA : Using ILA Probe P1

03:47

ILA : Using ILA Probe P2

11:41

ILA P1

00:16

ILA : Understanding Communication Protocol P1

04:52

ILA : Understanding Communication Protocol P2

05:24

Code

00:22

Profiling

6 lectures

Agenda

00:40

Profiling with AXI Timer

06:34

Code

00:26

Profiling with 64-bit Global Timer

06:29

Code

00:15

Understanding Profiling feature of SDK

12:04

Getting started with Interrupts

18 lectures

Agenda

00:25

Interrupts

01:30

Fundamentals of Interrupt Driver

12:31

Using GPIO Interrupt P1

04:58

Using GPIO Interrupt P2

05:54

Using GPIO Interrupt P3

16:22

Code

00:32

Using Multiple Interrupts P1

03:38

Using Multiple Interrupts P2

22:01

Code

00:38

Using AXI TImer Interrupt

10:04

Code

00:25

Using Interrupts with SCU Timer

17:01

Code

00:26

Using Interrupts with WDT

12:38

Code

00:27

Using Interrupt with TTC

11:01

Code

00:32

Memory Resources

8 lectures

Agenda

00:30

Using AXI BRAM with pointers P1

08:18

Using AXI BRAM with pointers P2

17:10

Understanding XIL_IO Drivers

09:47

BRAM RTL Simulation

08:56

Handling DDR Transactions

13:15

Code

00:20

Handling DDR to BRAM Transactions

11:24

Common Errors

2 lectures

AP transaction error, DAP status f0000021

02:52

fatal error: xil_printf.h: No such file or directory

04:59

Path Ahead: Building Custom AXI Peripherals for ZYNQ

1 lectures

Course Link

00:00

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