Mô tả

This Course will let you know about "How to Design FPGA based Signal Processing Projects on MATLAB/Simulink".

This course is on Designing FPGA based Signal Processing Projects with MATLAB/Simulink and FPGA Design Tool (Xilinx VIVADO/ISE), we are going to use Xilinx System Generator (interface between MATLAB/Simulink and VIVADO/ISE) and HDL Coder. From this two tools we can design our projects on traditional MATLAB/Sumilink design flow; using Blocks and integrating blocks in Simulink or using MATLAB codes and finally converting this two types of design in to HDL or into Bitstream so we can program FPGA from MATLAB/Simulink or VIVADO/ISE.

We have session on FIR,IIR, LMS Filter Design and OFDM Modulation algorithm implementation on FPGA.

MATLAB & Simulink are the best tools for Signal Processing Projects, while FPGA are best hardware platform for such type of Signal Processing Projects cause of it's flexibility and processing capabilities.

Bạn sẽ học được gì

FPGA Development with Matlab and Simulink Tool.

Creating Projects with System Generator and HDL coder

Implementing FIR and IIR Filter on FPGA from System Generator

Implementation of OFDM modulation on FPGA

Zynq FPGA Design with Matlab/Simulink (System Generator)

LMS filter design with HDL coder from Matlab

Yêu cầu

  • Basic Idea of Matlab and Simulink
  • FPGA Design Basics
  • Idea of FPGA Design with Xilinx ISE and VIVADO
  • Idea of Hardware Description Language

Nội dung khoá học

7 sections

Section_1 Installation of Matlab/Simulink and VIVADO/ISE

2 lectures
Installation of Matlab/Simulink and VIVADO/ISE
09:58
Section 1 Lab 1 Basic Design with Simulink Environment
04:59

Section_2 Introduction to HDL Coder and System Generator

2 lectures
Introduction to HDL Coder and System Generator Part I
07:27
Introduction to HDL Coder and System Generator Part II
18:38

Section_3 Project with System Generator

5 lectures
Section_3 Basic Project with System Generator Overview
09:45
Section 3 Lab 30 Basic Project with System Generator
12:03
Lab 31 Basic FFT Design with System Generator
20:31
Lab 32 Creating Custom JTAG Configuration
07:50
(Optional) Section_3 Lab 32 Demo: JTAG Implementation on Spartan 3E from Sys Gen
00:31

Section_4 Advance Design with HDL Coder

2 lectures
Section 4 Advance Design with HDL Coder Overview
19:36
LMS Filter Design_Advance Design with HDL Coder
11:44

Section_5 Advanced Design with System Generator

3 lectures
Lab 51 FIR Filter Design
12:49
OFDM Transceiver Design and Simulation Part I Transmitter Section
15:15
OFDM Transceiver Design and Simulation Part II Receiver Section & Simulation
14:00

Section_6 Zynq Development with System Generator & VIVADO

1 lectures
ZedBoard XADC+ Pmod Interfacing and Implementation on System Generator
07:04

Bonus Lecture + Vitis Model Composer(VMC)

2 lectures
Vitis Model Composer for 2021 or later Vitis
00:38
Bonus Lecture
00:25

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