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High-Level Synthesis for FPGA, Part 2 - Sequential Circuits

High-Level Synthesis for FPGA, Part 2 - Sequential Circuits

Loại khoá học: Hardware

Logic Design with Vitis-HLS

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50.000 VND
1.399.000 VND
Đầy Đủ Bài Giảng
Học Online Tiện Lợi
Kích Hoạt Nhanh 2-5 Phút
Thanh toán tự động
Được phép tải xuống

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Đánh giá

Mô tả

This course is an introduction to sequential circuits design in high-level synthesis (HLS). The goals of the course are describing, debugging and implementing sequential logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog).

It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. The course mainly uses the Xilinx Vitis-HLS toolset to describe, simulate and synthesise a high-level design description into the equivalent HDL code. The course also explains how to use the Integrated Logic Analyser (ILA) IP in Vivado to perform real-time debugging on the Basys3 board.

This course is the first of its kind that builds the HLS design flow and skills along with the digital logic circuit concepts from scratch. Along the course, you will follow several examples describing the HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches. In addition, the course utilises three exciting projects to put all the explained concepts together to design real circuits and hardware controllers.

This course is the second of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on sequential circuits, the first course explains how to describe combinational circuits in HLS. The other courses in the series will explain how to use HLS in designing advanced logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.

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16 sections

Prologue

2 lectures
Introduction
05:55
Course Structure
06:34

HW/SW Setup

5 lectures
Introduction
02:11
Vivado-HLX
04:49
Vivado and Vitis-HLS
04:14
Install Vivado HLx
05:01
Test Installation
07:20

D Flip-Flop (DFF)

10 lectures
Introduction
03:43
Memory Cell
03:57
Sequential Circuits
05:55
Clock Signal
04:56
State Concept
03:32
Reset Signal
04:37
Register
03:57
DFF LAB01
08:36
DFF LAB02
07:16
Exercises
00:57

Single Cycle Design Flow

7 lectures
Introduction
03:05
Definition and Idea
03:04
Parallel to Serial
06:54
Serial to Parallel
06:29
IP-Centric Design Flow
03:45
Parallel-Serial-Parallel LAB
17:57
Exercises
01:37

Testbench 01

6 lectures
Introduction
02:38
Definition
04:33
Parallel to Serial Testbench
03:27
Serial to Parallel Testbench
06:52
Input Waveform
05:08
Exercises
00:18

State Machine

7 lectures
Introduction
03:10
Definition
03:13
Concepts
03:32
Template
04:44
Combination Lock-VitisHLS
09:42
CombinationLock-Vivado
08:32
Exercises
00:15

Utilities

9 lectures
Introduction
03:36
Timer
07:56
Debouncer
10:36
Counter
13:02
Clock Generator
08:01
Pulse Generator
06:19
Single-Cycle Regular Pulses
06:31
Edge Detector
06:02
Exercises
00:16

Vending Machine

5 lectures
Introduction
02:47
Definition
05:23
Vitis-HLS
10:42
Vivado
11:49
Exercises
00:07

Integrated Logic Analyzer (ILA)

4 lectures
Introduction
02:47
Definition
06:05
Vivado
08:51
Exercises
00:12

Function Pipelining

7 lectures
Introduction
03:14
Definition
05:06
Multi-Cycle Design
06:57
Pipeline Design
05:43
Performance Metrics
04:07
IIR Example
09:31
Exercises
00:45

Seven Segments

7 lectures
Introduction
02:55
Definition
02:29
7Segment Driver
02:51
7Segment HLS
15:34
7Segment Vivado
05:49
Four-Digit Counter
12:31
Exercises
00:14

PMOD

5 lectures
Introduction
02:40
Definition
02:35
PMOD LED
06:49
PMOD Keyboard
10:54
Exercises
00:04

Interface Synthesis

10 lectures
Introduction
04:25
SCII Proc&Cons
03:35
Definition
05:19
Interface Synthesis
05:12
Block Level ap_ctrl_hs
04:20
Block Level ap_ctrl_hs: vitis-hls
19:29
Port Level ap_vld
03:01
Port Level ap_ack
02:44
Port Level ap_hs
02:46
Exercises
00:08

Project 1: Digital Dice

5 lectures
Introduction
02:36
Definition
01:47
Counter Based
11:09
LFSR
10:48
Exercises
00:07

Project 2: UART

6 lectures
Introduction
02:42
Definition
04:25
Design Structure and HLS
02:19
Transmitter-VitisHLS+Vivado
20:45
Receiver-VitisHLS+Vivado
18:00
Exercises
00:09

Project 3: Stepper Motor

7 lectures
Introduction
02:59
Definition
07:55
One-Phase-On: Vitis-HLS
12:56
Two-Phase-On: Vitis-HLS
07:46
Two-Phase-On with Control: Vitis-HLS
09:37
One&Two-Phase-On (Half Step): Vitis-HLS
06:59
Exercises
00:08

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