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UVM for Verification Part 1 : Fundamentals

UVM for Verification Part 1 : Fundamentals

Loại khoá học: Hardware

Step by Step Guide for building Verification Environment from Scratch

50.000 VND

85 VND

Đầy Đủ Bài Giảng

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Kích Hoạt Nhanh 2-5 Phút

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Mô tả

Writing Verilog test benches is always fun after completing RTL Design. You can assure clients that the design will be bug-free in tested scenarios. As System complexity is growing day by day, System Verilog becomes a choice for verification due to its powerful capabilities and reusability helping verification engineers quickly locate hidden bugs. The System Verilog lags structured approach whereas UVM works very hard on forming a general skeleton. The addition of the configuration database Shifts the way we used to work with the Verification Language in the past. Within a few years, verification engineers recognize the capabilities of UVM and adopted UVM as a defacto standard for the RTL Design verification. The UVM will have a long run in the Verification domain hence learning of UVM will help VLSI aspirants to pursue a career in this domain.

The course will discuss the fundamentals of the Universal Verification Methodology. This is a Lab-based course designed such that anyone without prior OOPS or system Verilog experience can immediately start writing UVM components such as Transaction, Generator, Sequencer, Driver, monitor, Scoreboard, Agent, Environment, Test. Numerous coding exercises, projects, and simple examples are used throughout the course to build strong foundations of the UVM.

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Fundamentals of Universal Verification Methodology

Reporting Macros and associated actions

UVM Object and UVM Component

UVM Phases

TLM Communication

Sequences

UVM Debugging features

Building UVM Verification Environment from Scratch

Yêu cầu

Fundamentals of SystemVerilog Testbench Environment

Nội dung khoá học

11 sections

How to use IDE

7 lectures

Series Intro

01:28

Agenda

00:35

Use this code for understanding IDE's

00:03

EDAplayground Link

00:00

Working with EDAP

07:52

Working with Vivado

05:21

Working with Questa

03:06

Reporting Mechanism

28 lectures

Agenda

00:55

Different Reporting Macros

06:26

Working with Reporting Macros

09:19

Code

00:05

Priniting Values of Variables without automation

02:30

Code

00:05

Working with Verbosity Level

10:02

Code

00:05

Working with Verbosity Level and ID

09:30

Code

00:12

Working with Individual Component

06:14

Code

00:20

Working with Hierarchy

06:17

Code

00:24

Other Reporting Macros

06:12

Code

00:12

Changing Severity of Macros

06:17

Code

00:16

Changing Associated Actions of Macros

06:57

Working with quit_count and UVM_ERROR

06:07

Code

00:16

Working with log file

06:28

Code

00:18

A11

1 question

A12

1 question

A13

1 question

A14

1 question

A15

1 question

Getting Started with Base Classes : UVM_OBJECT

38 lectures

Agenda

01:29

Fundamentals P1

06:00

Fundamentals P2

00:54

Fundamentals P3

05:55

Target

00:31

Creating Class

02:33

Deriving class from UVM_OBJECT

10:14

Using Field Macros P1 : INT

08:02

Code

00:10

Using Field Macros P2 : INT cont

06:35

Code

00:12

Using Field Macros P2 : ENUM, REAL

05:36

Code

00:15

Using Field Macros P3 : OBJECT

06:05

Code

00:15

Using Field Macros P4 : Arrays

09:04

Code

00:22

Copy and Clone Method

07:52

Code

00:15

Shallow Vs Deep Copy

07:31

Code

00:19

Copy and Clone Method

04:42

Code

00:20

Compare Method

04:17

Code

00:14

Create Method

03:21

Code

00:11

Factory Override : new vs create method

10:32

Code

00:20

do_print Method

06:35

Code

00:15

convert2string method

04:54

Code

00:20

do_copy method

05:34

Code

00:21

do_compare

08:48

A21

1 question

A22

1 question

UVM_COMPONENT

7 lectures

Agenda

00:56

Understanding UVM_TREE

05:04

Creating UVM_COMPONENT class

10:37

Code

00:13

Creating UVM_TREE P1

11:42

Creating UVM_TREE P2

03:34

Code

00:29

config_db

9 lectures

Agenda

00:26

Understanding typical format of config_db

12:01

Code

00:24

Demonstration P1

04:39

Demonstration P2

12:21

Demonstration P3

04:37

Demonstration P4

03:08

Used Case

09:14

Code

00:56

UVM_PHASES

32 lectures

Agenda

01:07

Fundamentals of Phases

01:50

Classification of Phases : Methods Used

03:57

Classification of Phases : Specific Purposes P1

02:20

Classification of Phases : Specific Purposes P2

03:41

Classification of Phases : Specific Purposes P3

01:38

Classification Summary

03:52

How we override phases

08:34

Code

00:34

Understanding execuction of build_phase in multiple components

12:13

Code

00:36

Understanding execution of connect_phase

04:10

Code

00:40

Execution of Multiple instance phases

04:16

Raising Objection

07:41

Code

00:11

How Time consuming phases works in Single Component

03:35

Code

00:16

Time Consuming phases in multiple components

06:52

Code

00:47

Timeout

05:58

Code

00:19

Drain Time : Individual Component

05:39

Code

00:22

Drain Time : Multiple Components

05:29

Code

00:56

Phase Debug

02:19

Phase Debug Switch

00:00

Objection Debug

02:37

Objection Debug Switch

00:00

A51

1 question

FAQ

00:42

TLM

20 lectures

Agenda

01:03

Fundamentals

11:18

Blocking PUT Operation P1

13:00

Code

00:35

Adding IMP to Blocking PUT Operation

08:11

Code

00:44

Port to IMP

07:38

Code

00:45

PORT-PORT to IMP

09:14

Code

01:00

Port to Export-IMP

06:34

Code

01:00

Get Operation

08:06

Code

00:47

Transport Port

09:09

Code

00:53

Analysis Port

10:33

Code

00:59

A71

1 question

A72

1 question

Sequence

24 lectures

Agenda

00:39

Fundamentals

05:50

Creating Sequences

17:10

Code

01:04

Understanding Flow

11:20

Code

01:26

Sending Data to Sequencer

08:53

Code

01:02

Sending Data to Driver Method 2 P1

04:24

Sending Data to Driver Method 2 P2

03:09

Code

01:07

Multiple Sequence in Parallel

09:56

Code

01:19

Changing Arbitration Mechanism P1

06:31

Changing Arbitration Mechanism P2

06:34

Code

01:26

Ways to Hold access of Sequencer

04:11

Holding Access of Sequencer P1

09:05

Code

01:16

Holding access of Sequencer P2 : Priority

02:44

Code

01:16

Holding access of Sequencer P3 : Lock Method

04:05

Code

01:17

Code

01:17

Projects : Combinational Adder

15 lectures

Agenda

00:39

Summary of the Verification Environment

04:31

Verification of Combinational adder : DUT

01:45

Transaction Class

03:54

Sequence Class

02:46

Driver Class

04:39

Monitor Class

03:27

Scoreboard Class

02:18

Agent Class

01:21

Environment Class

00:49

Test Class

01:05

Testbench Top

02:54

DUT + Interface

00:06

Testbench

02:10

A91

1 question

Projects : Verification of Sequential Adder

9 lectures

Design + Interface

01:07

Transaction + Generator

01:38

Driver

02:13

Monitor + Scoreboard

02:03

Agent + ENV + TEST

00:25

Testbench Top

02:13

DUT + Interface

00:10

Testbench

02:22

A101

1 question

Bonus Internship Program

1 lectures

Remote Internship Program

00:07

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