Mô tả

FPGA's are everywhere with their presence in the diverse set of the domain is increasing day by day. The two most popular Hardware description languages are VHDL and Verilog each having its unique advantage over the other. The best part about both of them is once you know one of them you automatically understand the other and then the capabilities of both worlds can be used to build complex systems. The course focus on the VHDL language. The curriculum is framed by analyzing the most common skills required by most of the firms working in this domain.  Most of the concepts are explained considering practical real examples to help to build logic.

The course illustrates the usage of  Modeling style, Blocking and Non-blocking assignments, Synthesizable FSM, Building Memories with Block and Distribute Memory resources, Vivado IP integrator, and Hardware debugging techniques such as ILA and VIO. The course explores FPGA Design flow with the Xilinx Vivado Design suite along with a discussion on implementation strategies to achieve desired performance. Numerous projects are illustrated in detail to understand the usage of the Verilog constructs to interface real peripheral devices to the FPGA. A separate section on writing Testebench and FPGA architecture further builds an understanding of the FPGA internal resources and steps to perform verification of the design.

Bạn sẽ học được gì

Fundamentals of VHDL Programming that will help to ace RTL Engineer Job Interviews.

Understand Vivado Design Suite flow for Digital System Design.

How to write an RTL for Synthesis

Different Modelling Styles in Hardware Description Language , Concurrent and Sequential Statements in VHDL

How to use Xilinx IP's and create Custom IP's.

IP integrator Design flow of the Vivado.

Writing VHDL Test benches.

Hardware Debugging in Vivado viz. Integrated Logic Analyzer, Virtual I/O.

From Zero to Hero in VHDL

Yêu cầu

  • Fundamental of Digital Circuit will give an added advantages.

Nội dung khoá học

19 sections

Installing Vivado

7 lectures
Agenda
00:30
Read this before downloading newer version of Vivado : 2020.2 or higher
00:03
How to Download, Install Vivado Design suite and add License.
09:45
Xilinx Vivado Webpack LIC FILE
00:00
How to verify License Installation
03:45
Adding boards such as Nexys 4 DDR which are not available in the Vivado
03:39
Common Error with Vivado: Incorrect Microsoft Visual C++ redistributable package
00:17

Performance Comparison ( Motivation)

7 lectures
Agenda
00:54
Demonstration of Parallel architecture usage
04:54
Ease of working with FPGA's
06:41
User Programmable I/O of FPGA vs MCU
00:51
Comparing Temporary storage
03:33
Whether Coding Guidlines really matters?
09:24
How to buy FPGA board in India (without paying Custom duty and GSTN no.)
04:36

Frequently Asked Questions

1 lectures
Q1
01:23

Vivado Design Flow P1

13 lectures
Agenda
00:57
Design Flow P1
07:04
Design Flow P2
09:12
Design Flow P3
14:23
Design flow P4
08:02
Design Flow P5
08:48
Summary of Design Flow
09:03
First Look at VHDL Code
16:51
Insights P1
06:31
Insights P2
04:08
Use of RTL analysis
00:23
Use of Post-Synthesis View
00:11
Assignment 1
1 question

Vivado Design Flow Part 2

13 lectures
Agenda
01:48
Understanding I/O Planning Project
04:59
Understanding Synthesis Settings
08:46
Clock Gating
02:22
Fundamentals of FSM Encoding
01:23
Vivado default Synthesis Configuration
Processing..
FSM Encoding Technique
01:04
Understanding Implementation Strategies of VIVADO
12:34
Code
00:23
Complete FPGA Design Flow P1
05:56
Complete Design flow P2
12:22
Code
01:56
Perform Complete Design flow.
1 question

Fundamentals : Signal and Variable

11 lectures
Agenda
01:55
Fundamentals Signal and Variable P1
11:28
Fundamentals Signal and Variable P2
03:52
Format of Signal and Variable
03:46
Datatypes in VHDL
01:58
Using Built-in datatype
07:49
Using Non-builtin datatypes
03:30
Using User defined datatypes
02:27
Using Signal
09:50
Using Variable
07:04
Initialization of Variable
06:23

Dataflow Modeling Style

24 lectures
Agenda
03:01
Different Modeling Style
16:10
Dataflow Modeling Style Fundamentals
04:20
Operators in Dataflow Modeling Style
06:03
Assignment Operator in Dataflow Modeling Style
03:59
Implementation of Half adder
06:14
Implementation of Full adder
09:59
Handling Multibit vectors P1
06:29
Handling Multibit vectors P2
03:09
Shift Operators Fundamentals
14:33
Shift Operator Demonstration
11:39
Rotation Operator Fundamentals
03:24
Rotation Operator Demonstration
05:55
Arithmetic Operator Fundamentals
07:44
Arithmetic Opertation : Unsigned Type
08:16
Arithmetic Opertation : Std_logic_Vector Type
08:33
Understanding type-conversion function
11:12
type-conversion Demonstration
08:22
Conditional and Selected Signal Statement
04:55
Conditional and Selected Signal Statement
12:21
Implement Half Subtractor using Dataflow modeling style.
1 question
Implement 4:1 Mux with Dataflow Modeling Style
1 question
Implement 4-bit Gray to Binary Code Converter
1 question
Performing Division
1 question

Behavioral Modeling Style

24 lectures
Agenda
00:58
Understanding Process block
06:04
Behavioral Modeling Style Skeleton
06:46
Understanding IF ELSE P1
06:10
Understanding IF ELSE P2
08:06
Good Practices : IF ELSE P1
03:59
Good Practices : IF ELSE P2
03:27
D-Flipflop with Synchronus Reset
06:59
D-Flipflop with Asynchronus Reset
02:35
Simulation : Asynchronus Reset D-Flipflop
03:08
Simulation : Synchronus Reset D-Flipflop
02:57
Case Statement Skeleton
01:34
4:1 Mux with Case Statement
04:21
Binary to Seven Segment Decoder P1
07:18
Binary to Seven Segment Decoder P2
11:09
Binary to Seven Segment Decoder P3
00:48
Implementing Counter
11:13
Code
00:22
Right Circular Shifter P1
06:33
Right Circular Shifter P2
12:27
Code
00:33
Design 8:1 Mux with Behavioral Modeling Style
1 question
Design 8:3 Priority Encoder
1 question
Design Universal Circular Shifter
1 question

Understanding Testbench

13 lectures
Ways to create Testbenches
06:05
Using Force Constant and Force Clock
08:52
VHDL TB Fundamentals P1 : Testbench Overview
10:59
VHDL TB Fundamentals P2 : Generating Random signals
09:25
Code
00:46
VHDL TB Fundamentals P3 : Generating Clock Signal
05:22
Code
00:43
Summary
03:35
Code
00:21
Example 1 : 4-bit Counter
10:33
Code
00:41
Example 2: Adder IP
13:05
Design a testbench code for Serial In Serial Out Shift Register
1 question

Structural Modeling Style

9 lectures
Target
02:42
Half adder
03:48
Full adder with Half adder
14:18
Code
00:28
Using Vivado IP Integrator : 4-bit Ripple Carry adder
15:22
Block Design
00:00
Johnson Counter with D FlipFlop
15:54
Design 32:1 Mux with the help of 8:1 Mux using Structural Modeling Style.
1 question
Design Ring Counter with the help of D Flipflop using Structural Modeling Style
1 question

Finite State Machines in VHDL

23 lectures
Target
09:00
State Machines
03:06
Mealy FSM : Three Process Methodolgy
15:22
Code
00:34
Mealy FSM : Two Process Methodology
03:16
Code
00:27
Mealy FSM : SIngle Process Methodology
04:42
Code
00:26
Moore FSM : Three Process Methodology
08:38
Code
00:30
Moore FSM : Two Process Methodology
03:03
Code
00:26
Moore FSM : Single Process Methodology
03:03
Code
00:24
Understanding Sequence Detector
11:47
Implementing Overlapping Sequence Detector
11:12
Code
00:33
Traffic Light Controller Flowchart
02:11
Understanding Traffic Light Controller
09:44
Code
00:39
Design Overlapping Sequence Detector to identify sequence 101
1 question
Design Non-Overlapping Sequence detector to detect sequence 1011
1 question
Write testbench to verify the functional behavior of the Sequence detector
1 question

Commonly Asked Question's from previous Module

2 lectures
What are alternatives to generate stimulis for Sequence detector ? ( Bishal )
17:05
Code
00:39

Use of IP's

6 lectures
Target
04:30
How we Create IP
13:42
How we refresh IP repository
08:16
How we add Customization Parameters to IP
08:17
Complete Design P1 : Barrel Shifter
09:57
Complete Design P2
14:11

Hardware Debugging

7 lectures
Undertanding ILA and VIO
09:58
Adding ILA core to design
12:19
Code
00:14
Analyzing Waveform with ILA
02:58
Adding Virtual I/O core to the design
13:31
Code
00:22
Analyzing response of the System with VIO
02:54

Memories in FPGA

12 lectures
Understanding Memories in FPGA
05:44
Distributed Memory Vs Block Memory
04:58
Max. Distributed and Block Memory Size
00:00
Creating Memory Method 1
11:36
Creating Memory Method 2
13:15
Creating Memory Method 3
08:26
Single Port RAM with Block Memory
17:07
Single Port RAM with Block Memory
00:21
Single Port RAM with Distributed Memory
08:24
Single Port RAM with Distributed Memory
00:19
Single Port ROM IP with Block Memory and COE file
14:18
Signle Port RAM in VHDL with Testbench
25:56

Projects

1 lectures
Project Categories
01:56

Timing Domain Projects

2 lectures
Implementation of VGA Controller in VHDL
34:21
Source Code
01:40

Data dominant Projects

7 lectures
P1 : Implementing 4-bit Barrel Shifter with Rotate Logic
29:46
System Implementation : 4-bit Barrel Shifter
00:00
P2 : Implementation of Universal Serial Asynchronus Transmitter(UART) with VHDL
46:10
Flowchart and Code
00:42
Implementation of SPI for DAC PMOD DA4 in VHDL
37:18
Code
00:50
Implementing Parallel Interface for Interfacing LCD with FPGA
00:50

Fundamental of FPGA architecture

13 lectures
Need of Reprogrammable architecture
07:09
PLD Classification
03:32
Understanding Programmable Logic in PROM
06:11
PROM Demonstration on NI Multisim IDE
08:01
PAL and PLA
04:12
SPLD and GAL
05:38
Understanding GAL Datasheet : 16V8
03:32
SPLD and GAL Summary
03:45
CPLD architecture
05:38
Introduction to FPGA Architecture
08:08
Use of Wide Multiplexer
06:44
Spartan 6 Architecture
08:42
Spartan 6 FPGA Architecture Summary
04:02

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