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VSD - Physical Design Flow

VSD - Physical Design Flow

Loại khoá học: Design Tools

VLSI - Building a chip is like building a city!!

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50.000 VND
1.399.000 VND
Đầy Đủ Bài Giảng
Học Online Tiện Lợi
Kích Hoạt Nhanh 2-5 Phút
Thanh toán tự động
Được phép tải xuống

Tổng quan

Nội dung khoá học

Đánh giá

Mô tả

The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.

We have contributed anonymously to this website, just to share the part of knowledge learned all these years, with the students keen to learn the basic concepts of the Chip Design. And also shared our industrial experience to give the technological exposure of current development in chip world...

Bạn sẽ học được gì

Understand Industrial Physical Design Flow

Modify and Develop own Flow as per Specifications

Yêu cầu

  • Basic Digital Design

Nội dung khoá học

8 sections

Physical Design Flow Overview

5 lectures
Floor-Planning Steps
10:36
Netlist Binding And Placement Optimization
09:34
Placement Timing And Clock Tree Synthesis
09:26
Clock Net Shielding
09:34
Route - DRC Clean - Parasitics Extraction - Final STA
09:33

Floorplanning

5 lectures
Utilization Factor And Aspect Ratio
09:10
Concept Of Pre-Placed Cells
09:27
De-coupling Capacitors
10:08
Power Planning
10:26
Pin Placement And Logical Cell Placement Blockage
09:34

Placement

3 lectures
Net-list Binding And Placement
09:22
Optimize Placement Using Estimated Wire Length And Capacitance
10:02
Optimize Placement Conitnued
08:48

Timing Analysis With Ideal Clocks

5 lectures
Setup Timing Analysis And Introduction to Flip-Flop Setup Time
09:44
Introduction To Clock Jitter and Uncertainty
08:24
Setup Timing Analysis with Multiple Clocks
08:49
Multiple Clock Timing Analysis And Introduction To Data Slew Check
09:06
Data Slew Check
09:21

Clock Tree Synthesis And Signal Integrity

5 lectures
Clock Tree Routing And Buffering using H-Tree Algorithm
09:07
Crosstalk And Clock Net Shielding
09:24
Static Timing Analysis With Real Clocks
12:18
Hold Timing Analysis Concluded
10:11
Multiple Clocks Setup Timing Analysis With Real Clocks
08:17

Routing And Design Rule Check (DRC)

3 lectures
Introduction to Maze Routing - Lee's Algorithm
08:42
Lee's Algorithm Conclusion
09:52
Design Rule Check
09:53

Parasitics Extraction

4 lectures
Introduction to IEEE 1481 - 1999 SPEF format
09:20
SPEF Representation of a NET
08:15
Distributed Resistance And Capacitance Representation in SPEF
09:54
SPEF Header Description, Physical Design Flow Conclusion and What Next !!
08:22

Bonus - Technological advances happening in the world of opensource

1 lectures
Next Generation Education Technology for VLSI Design Flow
01:46:33

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