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Design
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VLSI
VSD - Signal Integrity

VSD - Signal Integrity

Loại khoá học: Design Tools

VLSI - Real and practical steps to build chip with minimum Signal Integrity issues!!

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50.000 VND
1.399.000 VND
Đầy Đủ Bài Giảng
Học Online Tiện Lợi
Kích Hoạt Nhanh 2-5 Phút
Thanh toán tự động
Được phép tải xuống

Tổng quan

Nội dung khoá học

Đánh giá

Mô tả

Performance, Power and Area are the three main pillars of the Chip Design, Crosstalk can hamper all three. 


Crosstalk is the interference caused due to communication between the circuits

Lets learn to " HOW TO REDUCE CROSSTALK ? " to achieve a efficient Chip design which give the best performance, uses optimal power and in minimal Chip area.

Course Details:
•Reasons for Crosstalk

•Introduction to Noise Margin

•Crosstalk Glitch Example

•Factors Affecting Glitch Height

•AC Noise Margin

•Timing Window Concepts

•Impact of Crosstalk on Setup and Hold Timing

•Techniques to reduce Crosstalk

•Power Supply Noise

Bạn sẽ học được gì

To Learn Chip Design with minimal Crosstalk in the circuits.

To Design a Chip with minimal errors.

Yêu cầu

  • Basic of VLSI and Chip Design

Nội dung khoá học

10 sections

Introduction

1 lectures
Introduction
08:16

Crosstalk - Why and How Crosstalk occurs in a CHIP ??

6 lectures
High Routing Density
09:55
Dominant Lateral Capacitance
09:29
Introduction to Noise Margin
08:39
Noise Margin Voltage Parameters
08:56
Noise Margin Equation and Summary
09:04
Lower Supply Voltage
10:12

Glitch Examples And Factors Affecting Glitch Height

7 lectures
Basic Crosstalk Glitch Example
09:58
Glitch Discharge With High Drive Strength NMOS Transistor
09:50
Glitch Discharge With High Drive Strength PMOS Transistor
10:16
Factors Affecting Glitch Height - Spacing
09:42
Factors Affecting Glitch Height - Aggressor Drive Strength
10:28
Factors Affecting Glitch Height - Victim Drive Strength
08:28
Factors Affecting Glitch Height - Conclusion
10:13

Tolerable Glitch Heights and Introduction to AC Noise Margin

7 lectures
Impacts Of Glitch
10:20
Introduction to Safe and Unsafe Glitches
09:43
Tolerable Glitch Heights using DC Noise Margin
09:12
Tolerable Glitch Heights using DC Noise Margin Continued
09:03
AC Noise Margin
08:29
Impact of Load on Glitch Height
09:02
Justification of Load Impact and Conclusion
09:00

Timing Windows

5 lectures
Single Victim Multiple Aggressors
09:41
Introduction to Timing Window
08:58
Timing Window Formation
09:21
Bucketization based on Timing Windows
09:28
Final Glitch Calculation
09:26

Crosstalk Delta Delay Analysis

7 lectures
Crosstalk Delta Delay - Aggressor Victim Switching in Opposite Direction
09:16
Impact of Crosstalk Delta Delay on Clock Skew
09:42
Setup Timing Analysis Using Real Clocks
10:13
Impact of Crosstalk Delta Delay on Setup Timing
09:14
Crosstalk Delta Delay - Aggressor Victim Switching in Same Direction
08:39
Hold Timing Analysis Using Real Clocks
09:19
Impact of Crosstalk Delta Delay on Hold Timing
08:27

Noise Protection Technique

3 lectures
Shielding
08:34
Spacing
09:04
Drive Strength
11:07

Power Supply Noise And Power Mesh Solution

5 lectures
Introduction To Power Supply Noise
11:18
Need of Decoupling Capacitors (DECAPS)
10:54
Power Supply Noise With Multiple Instantiations
08:39
Voltage Droop And Ground Bounce
09:12
Power Mesh Solution
07:06

Summary

1 lectures
Summary
08:15

Quiz and Evaluation

9 lectures
Which Capacitance is dominant for 0.1um and below process
1 question
What is the NMH and NML of the below Noise Curve ?
1 question
Which of the below scenario is correct ?
1 question
Which Scenario impacts the Victim "the least" ?
1 question
Mark Potentially Unsafe Glitches among the below !!
1 question
Identify Potentially Safe Glitches !!
1 question
which of below bucket/s are prone to glitch ?
1 question
What is the Setup Slack between 'A' and 'B' ? (Clock Period 'T' = 70ps)
1 question
What is Hold Slack between 'B' and 'C' ?
1 question

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